Semiconductor devices, such as semiconductor integrated circuits (ICs), include numerous semiconductor device structures. Example semiconductor device structures are interconnected complementary metal oxide semiconductor (CMOS) transistors, which include both P-channel and N-channel MOS transistors. Interconnectivity between various device structures is accomplished by metalized contacts forming interlayer connections between the device structures.
Semiconductor device structures, including CMOS transistors, are being designed to have smaller and smaller feature sizes (e.g., gate structures). Based on this trend, as the gate pitch becomes smaller, the contacts that connect the source/drain regions of the transistor with metalized contacts also become smaller. As the contacts decrease in size, there is an increase in contact resistance. Contact resistance, which is decided by contact area and sheet resistivity, is becoming a limiting factor in further device performance improvement.
One approach to reduce contact resistance is disclosed in U.S. Pat. No. 8,101,489. A semiconductor substrate having doped regions is provided. A pre-amorphous implantation process and neutral (or non-neutral) species implantation process is performed over the doped regions. Subsequently, a silicide is formed in the doped regions. By conducting a pre-amorphous implantation combined with a neutral species implantation, the contact resistance between the silicide contact area and source/drain substrate interface is reduced.
Another approach to reduce contact resistance is disclosed in U.S. Pat. No. 8,134,208. A semiconductor device includes a semiconductor device structure and a contact, and the contact is electrically and physically coupled to the semiconductor device structure at both a surface portion and a sidewall portion of the semiconductor device structure.
While the above approaches may be effective in reducing contact resistance, further improvements may be desired.